//this is a module that help to initial and record values of hash
//by yja
//2021/4/27

module Registers1 (
    input wire clk,
    input wire rst_n,
    input wire reg_en,
    input wire[31:0] data_in,

    output wire[31:0] data_out
);

reg[31:0] register;

assign data_out = register;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        register <= 32'b0;
    end else if(reg_en) begin
        register <= data_in;
    end
end

endmodule